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<div class="header">
  <div class="headertitle"><div class="title">ADC (Analog Digital Converter)<div class="ingroups"><a class="el" href="group__group__hal__impl.html">CAT1 Implementation Specific</a></div></div></div>
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<h1><a class="anchor" id="cyhal_adcmic_impl_features"></a>
Features</h1>
<p >The CAT1B ADC supports the following features:</p><ul>
<li>Resolution: 16 bit</li>
<li>Sample rate: Fixed 480 ksps</li>
<li>Minimum acquisition time: Up to 2084 ns</li>
<li>SW-based async transfer only (DMA is not supported)</li>
<li>VREF: <a class="el" href="group__group__hal__adc.html#ggad77d58d52432f1f68f869b047b1a9bbeac3e8e93e60d21bfe83545ac9e4f8ca15">CYHAL_ADC_REF_INTERNAL</a> (1.8V) only</li>
<li>Only <a class="el" href="group__group__hal__general__types.html#gga246fde0e79029f514ce3846b31e366d7a6f0f4df45e9cac012a2c8e5ba736241b">CYHAL_POWER_LEVEL_DEFAULT</a> and <a class="el" href="group__group__hal__general__types.html#gga246fde0e79029f514ce3846b31e366d7a0f601c5d5843c59e58ee1988dd0e6861">CYHAL_POWER_LEVEL_OFF</a> are defined.</li>
<li>Single ended vneg: <a class="el" href="group__group__hal__adc.html#ggac9e066ac01bed2c374c3d0e164988d97a10b9c188fccf67e20b0fce8d6fef6bc0">CYHAL_ADC_VNEG_VSSA</a></li>
</ul>
<p >The following functions are not supported:</p><ul>
<li>Differential channels</li>
<li>Continuous scanning</li>
<li><a class="el" href="group__group__hal__adc.html#gga3e21dc2fe98693d72260411459e1fc6ca72cdd442365c9b501eb0144ef31beb83">CYHAL_ADC_EOS</a> event (this is only applicable when continuously scanning)</li>
<li>Averaging. In <a class="el" href="group__group__hal__adc.html#structcyhal__adc__config__t">cyhal_adc_config_t</a>, average count must be 1 and average_mode_flags must be 0. In <a class="el" href="group__group__hal__adc.html#structcyhal__adc__channel__config__t">cyhal_adc_channel_config_t</a>, enable_averaging must be false.</li>
<li>External vref and bypass pins</li>
<li></li>
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